A signal receiving circuit receiving a signal with a phase variation includes a signal receiving circuit that receives a signal of DDR memory interface. The DDR (Double Data Rate) memory inputs and outputs data at both of the positive edge and the negative edge of the clock (CK), and transfers data at a data transfer rate twice as fast as the clock frequency.
In such a memory, an internal CK signal generated in the memory controller is transmitted to a DIMM (Dual In-line Memory Module). Based on the CK signal, the DIMM generates a data strobe (DQS) signal, and transmits the DQS signal and data (DQ) signals to the main controller. On the main controller side, a signal receiving circuit receives the DQS signal and the DQ signals. The signal receiving circuit performs retiming on the DQ signals using the DQS signal, and transfers the clock source to an internal clock. In this case, in order to reliably receive the data signals by latch circuits at a receiving point, it is desired that timing relationships between the internal CK signal and the receiving data signals are within a certain range.
With respect to the reception of the signal by the memory controller, it is known that a clock phase different from that of the reference clock is generated and the data strobe signal is delayed (see, for example, Japanese National Publication of International Patent Application No. 2007-536773).
It is known that first and second timings which are the delayed data strobe signal are generated and by selectively using those two timing signals, a signal ambiguous state is avoided (see, for example, Japanese Laid-open Patent Publication No. 2006-107352).
Further, it is known that, in the memory controller, the read data are taken in at a change edge of the data strobe signal (see, for example, Japanese Laid-open Patent Publication No. 11-25029).
Further, it is known that a phase difference between the data strobe signal and the read clock is measured, and by adjusting the delay time of the clock signal using the phase difference to synchronize with the clock signal, the data signal is taken in (see, for example, Japanese Laid-open Patent Publication No. 2008-71018).